A synchronous memory as the background art and its timing chart are shown in FIGS. 22 and 23, respectively. 10 A row address is applied to a latch 12 and is latched in synchronism with a synchronizing signal .phi.. After the latch time t.sub..lambda.at, this signal is applied to a row decoder 11. After an address decode time t.sub.dec, the row decoder 11 applies a row decoded signal to a memory cell array 14 through one of the corresponding word lines 13, 13, ... On the other hand, a column address is applied to a latch 17, and is latched in synchronism with the synchronizing signal .phi.. After the latch time t.sub..lambda.at, this signal is applied to a column decoder 16. After the address decode time t.sub.dec, the column decoder 16 applies a column decoded signal to an input/output circuit 19 to select one of corresponding bit lines 18, 18, When the row decoded signal is thus outputted to the corresponding word line 13, and the corresponding bit line 18 is selected in accordance with the column decoded signal, data from the memory cell array 14 is read out to the data line 20 after a sense time t.sub.sense, with the data setup time t.sub.ds being ensured. The above-mentioned cycles are repeatedly executed. Thus, the readout of data corresponding to the respective addresses is sequentially executed.
Each of a series of cycle times t.sub.cycle is expressed as follows: EQU t.sub.cycle =t.sub..lambda.at +t.sub.dec +t.sub.sense +t.sub.ds( 1)
It is seen from the above equation (1) and FIG. 23 that the address decode time t.sub.dec occupies a large ratio with respect to the entire cycle time t.sub.cycle.
It is very important for the realization of a high speed memory to shorten the access time of the memory. Especially, for a high speed memory such as a high speed SRAM, etc., it is very advantageous that the cycle time be shortened.